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WED9LC6416V
128Kx32 SSRAM/4Mx32 SDRAM
FEATURES
s Clock speeds: * SSRAM: 200, 166,150, and 133 MHz * SDRAMs: 125 and 100 MHz s DSP Memory Solution * Texas Instruments TMS320C6201 * Texas Instruments TMS320C6701 s Packaging: * 153 pin BGA, JEDEC MO-163 s 3.3V Operating supply voltage s Direct control interface to both the SSRAM and SDRAM ports on the "C6x" s Common address and databus s 65% space savings vs. monolithic solution s Reduced system inductance and capacitance
Advanced*
External Memory Solution for Texas Instruments TMS320C6000 DSP DESCRIPTION
The WED9LC6416VxxBC is a 3.3V, 128K x 32 Synchronous Pipeline SRAM and a 4Mx32 Synchronous DRAM array constructed with one 128K x 32 SBSRAM and two 4Mx16 SDRAM die mounted on a multilayer laminate substrate. The device is packaged in a 153 lead, 14mm by 22mm, BGA. The WED9LC6416VxxBC provides a total memory solution for the Texas Instruments TMS320C6201 and the TMS320C6701 DSPs The Synchronous Pipeline SRAM is available with clock speeds of 200, 166,150, and 133 MHz, allowing the user to develop a fast external memory for the SSRAM interface port . The SDRAM is available in clock speeds of 125 and 100 MHz, allowing the user to develop a fast external memory for the SDRAM interface port . The WED9LC6416V is available in both commercial and industrial temperature ranges.
* This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice.
FIG. 1
1 A B C D E F G H J L M N P R T U
PIN CONFIGURATION TOP VIEW
2 DQ23 DQ22 VCCQ DQ21 DQ20 VCCQ NC NC A7 NC VCCQ DQ11 DQ10 VCCQ DQ9 DQ8 2 3 VCC VCC VCC VCC VCC VCC NC A8 A9 NC VCC VCC VCC VCC VCC VCC 3 4 VSS VSS VSS VSS VSS VSS VSS VSS BWE2 BWE0 VSS VSS VSS SSOE 4 5 VSS SDCE VSS SDCLK VSS VSS VSS VSS BWE3 BWE1 VSS SSCLK VSS SSCE 5 6 VSS VSS NC VSS VSS VSS VSS NC NC NC NC NC VSS VSS VSS NC NC 6 7 VCC VCC VCC VCC VCC VCC A2 A1 A0 NC NC VCC VCC VCC VCC VCC VCC 7 8 DQ24 DQ25 VCCQ DQ26 DQ27 VCCQ A4 A3 A11 A13 A15 VCCQ DQ4 DQ5 VCCQ DQ6 DQ7 8 9 DQ28 DQ29 VCCQ DQ30 DQ31 VCCQ A5 A10 A12 A14 A16 VCCQ DQ0 DQ1 VCCQ DQ2 DQ3 9 VSS NC A B C D E F G H J K L M N P R T U SSCE SDCE VCC VCCQ
PIN DESCRIPTION
A0-16 DQ0-31 SSCLK SSADC SSWE SSOE SDCLK SDRAS SDCAS SDWE SDA10 BWE0-3 Address Bus Data Bus SSRAM Clock SSRAM Address Status Control SSRAM Write Enable SSRAM Output Enable SDRAM Clock SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Write Enable SDRAM Address 10/auto precharge SSRAM Byte Write Enables SDRAM SDQM 0 - 3 Chip Enable SSRAM Device Chip Enable SDRAM Device Power Supply pins, 3.3V Data Bus Power Supply pins, 3.3V (2.5V future) Ground No Connect
DQ19 DQ18 VCCQ DQ17 DQ16 VCCQ NC NC A6 NC VCCQ DQ12 DQ13 VCCQ DQ14 DQ15 1
SDWE SDA10
SDRAS SDCAS
K NC / A17 NC / A18 NC / A19
SSADC SSWE
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FIG. 2
BLOCK DIAGRAM
A0-16
A0 A1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 BWE BW1 BW2 BW3 BW4 CE2 OE ADSC CLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A10/AP BA0 BA1 LDQM UDQM CS RAS CAS WE CLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A10/AP BA0 BA1 LDQM UDQM CS RAS CAS WE CLK
DQ1-8 DQ9-16 DQ17-24 DQ25-32
DQ0-7 DQ8-15 DQ16-23 DQ24-31
SSWE BWE0 BWE1 BWE2 BWE3 SSCE SSOE SSADC SSCLK
DQ0-31
DQ0-7 DQ8-15
DQ0-7 DQ8-15
SDA10
A12 A13
SDCE SDRAS SDCAS SDWE SDCLK
DQ0-7 DQ8-15
DQ16-23 DQ24-31
A12 A13
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OUTPUT FUNCTIONAL DESCRIPTIONS
Symbol SSCLK SSADS SSOE SSWE SSCE SDCLK SDCE SDRAS SDCAS SDWE Type Input Input Input Input Input Input Signal Pulse Pulse Pulse Pulse Pulse Pulse Polarity Function
Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock. Active Low Active Low Active Low Active Low When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation to be executed by the SSRAM. SSCE disable or enable SSRAM device operation. SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3. When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation to be executed by the SDRAM. Address bus for SSRAM and SDRAM A0 and A1 are the burst address inputs for the SSRAM During a Bank Active command cycle, A0-11, SDA10 defines the row address (RA0-10) when sampled at the rising clock edge.
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
A0-16, SDA10
Input
Level
--
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A12 and A13 define the bank to be precharged. If SDA10 is low, autoprecharge is disabled. During a Precharge command cycle, SDA10 is used in conjunction with A12 and A13 to control which bank(s) to precharge. If SDA10 is high, all banks will be precharged regardless of the state of A12 and A13. If SDA10 is low, then A12 and A13 are used to define which bank to precharge.
DQ0-31 BWE0-3
Input Output Input
Level Pulse
--
Data Input/Output are multiplexed on the same pins. BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31. Power and ground for the input buffers and the core logic. Data base power supply pins, 3.3V (2.5V future).
Vcc, Vss VCCQ
Supply Supply
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ABSOLUTE MAXIMUM RATINGS
Voltage on Vcc Relative to Vss Vin (DQx) Storage Temperature (BGA) Junction Temperature Short Circuit Output Current -0.5V to +4.6V -0.5V to Vcc +0.5V -55C to +125C +175C 100 mA
RECOMMENDED DC OPERATING CONDITIONS
(VCC = 3.3V -5% / +10% unless otherwise noted; 0C TA 70C, Commercial; -40C TA 85C, Industrial)
Parameter Supply Voltage (1) Input High Voltage (1,2) Input Low Voltage (1,2) Input Leakage Current 0 VIN Vcc Output Leakage (Output Disabled) 0 VIN Vcc Output High (IOH = -4mA) (1) Output Low (IOL = 8mA) (1) Symbol VCC VIH VIL ILI ILo VOH VOL Min 3.135 2.0 -0.3 -10 -10 2.4 -- Max 3.6 VCC +0.3 0.8 10 10 -- 0.4 Units V V V A A V V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTES: 1. All voltages referenced to Vss (GND). 2. Overshoot: VIH +6.0V for t tKC/2 Underershoot: VIL -2.0V for t tKC/2
(VCC = 3.3V -5% / +10% unless otherwise noted; 0C TA 70C, Commercial; -40C TA 85C, Industrial)
Description Power Supply Current: Operating (1,2,3) Conditions Symbol Frequency 133MHz 150MHz 166MHz 200MHz 133MHz 150MHz 166MHz 200MHz 83MHz 100MHz 125MHz Typ 400 450 500 550 300 350 400 450 220 235 255 20.0 Max 550 580 625 700 450 480 525 585 240 250 280 40.0 Units
DC ELECTRICAL CHARACTERISTICS
SSRAM Active / DRAM Auto Refresh
Icc1
mA
Power Supply Current Operating (1,2,3)
SSRAM Active / DRAM Idle
Icc2
mA
Power Supply Current Operating (1,2,3)
SDRAM Active / SSRAM Idle SSCE and SDCE Vcc -0.2V, All other inputs at Vss +0.2 VIN or VIN VCC -0.2V, Clk frequency = 0 SSCE and SDCE VIH min All other inputs at VIL max VIN or VIN VCC -0.2V, Clk frequency = 0
Icc3
mA
CMOS Standby
ISB1
mA
TTL Standby Auto Refresh
ISB2 Icc5
30.0 190
55.0 250
mA mA
NOTES: 1. ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading. 2. "Device idle" means device is deselected (CE VIH) Clock is running at max frequency and Addresses are switching each cycle. 3. Typical values are measured at 3.3V, 25C. ICC (operating) is specified at specified frequency.
BGA CAPACITANCE
Description Address Input Capacitance (1) Input/Output Capacitance (DQ) (1) Control Input Capacitance (1) Clock Input Capacitance (1) NOTE: 1. This parameter is sampled. Conditions TA = 25C; f = 1MHz TA = 25C; f = 1MHz TA = 25C; f = 1MHz TA = 25C; f = 1MHz Symbol CI CO CA CCK Typ 5 8 5 4 Max 8 10 8 6 Units pF pF pF pF
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(VCC = 3.3V -5% / +10% unless otherwise noted; 0C TA 70C, Commercial; -40C TA 85C, Industrial)
Symbol Parameter Clock Cycle Time Clock HIGH Time Clock LOW Time Clock to output valid Clock to output invalid Clock to output on Low-Z Clock to output in High-Z Output Enable to output valid Output Enable to output in Low-Z Output Enable to output in High-Z Address, Control, Data-in Setup Time to Clock Address, Control, Data-in Hold Time to Clock tKHKH tKLKH tKHKL tKHQV tKHQX tKQLZ tKQHZ tOELQV tOELZ tOEHZ tS tH 200MHz Min Max 5 1.6 1.6 2.5 1.5 0 1.5 3 2.5 0 3.0 1.5 0.5 166MHz Min Max 6 2.4 2.4 3.5 1.5 0 1.5 3.5 3.5 0 3.5 1.5 0.5 150MHz Min Max 7 2.6 2.6 3.8 1.5 0 1.5 3.8 3.8 0 3.5 1.5 0.5 133MHz Min Max 8 2.8 2.8 4.0 1.5 0 1.5 4.0 4.0 0 3.8 1.5 0.5 Units ns ns ns ns ns ns ns ns ns ns ns ns
SSRAM AC CHARACTERISTICS
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SSRAM OPERATION TRUTH TABLE
Operation Deselected Cycle, Power Down WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None External External External Current Current Current Current Current Current SSCE H L L L X X H H X H SSADS L L L L H H H H H H SSWE X L H H H H H H L L SSOE X X L H L H L H X X DQ High-Z D Q High-Z Q High-Z Q High-Z D D
NOTE: 1. X means "don't care", H means logic HIGH. L means logic LOW. 2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK. 3. Suspending burst generates wait cycle 4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH though out the input data hold time. 5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
SSRAM PARTIAL TRUTH TABLE
Function READ WRITE one Byte (DQ0-7) WRITE all Bytes SSWE H L L BWE0 X L L BWE1 BWE2 X H L X H L BWE3 X H L
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FIG. 3
SSRAM READ TIMING
t KHKH tKHKL tKLKH
SSCLK
tS tH
SSADS
tS
SSCE
tH
tS
ADDR
A1
A2
A3
A4
A5
tH
SSOE
t OEHQZ t OELQV
SSWE
t KHQX t KQLZ t KHQV
Q(A2) Q(A3) Q(A4) Q(A5)
DQ
Q(A1)
FIG. 4
SSRAM WRITE TIMING
t KHKH tKHKL tKLKH
SSCLK
tS tH
SSADS
tH
SSCE
tH
tS
ADDR
tH
A1
A2
A3
A4
A5
SSOE
tS
KHG WX
tH
SSWE
tH tS
DQ
D(A1)
D(A2)
D(A3)
D (A4)
D(A5)
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(VCC = 3.3V -5% / +10% unless otherwise noted; 0C TA 70C, Commercial; -40C TA 85C, Industrial)
Symbol Parameter Clock Cycle Time (1) CL = 3 CL = 2 tCC tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD Min 8 10 3 3 3 2 1 2 7 20 20 20 50 70 70 1 1 1 1.5 2 1 20 20 20 50 80 80 1 1 1 1.5 2 2 125MHz Max 1000 1000 6 Min 10 12 3 3 3 2 1 2 7 24 24 24 60 90 90 1 1 1 1.5 2 1 100MHz Max 1000 1000 7 Min 12 15 3 3 3 2 1 2 8 83MHz Max 1000 1000 8 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK ea
SDRAM AC CHARACTERISTICS
Clock to valid Output delay (1,2) Output Data Hold Time (2) Clock HIGH Pulse Width (3) Clock LOW Pulse Width (3) Input Setup Time (3) Input Hold Time (3) CLK to Output Low-Z (2) CLK to Output High-Z Row Active to Row Active Delay (4) RAS\ to CAS\ Delay (4) Row Precharge Time (4) Row Active Time (4) Row Cycle Time - Operation (4) Row Cycle Time - Auto Refresh (4,8) Last Data in to New Column Address Delay (5) Last Data in to Row Precharge (5) Last Data in to Burst Stop (5) Column Address to Column Address Delay (6) Number of Valid Output Data (7)
10,000
10,000
10,000
NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns (trise/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(trise = tfall)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self-refresh exit.
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CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHz SDRAM (Unit = number of clock)
Frequency CAS Latency 3 3 2 tRC 70ns 9 7 6 tRAS 50ns 6 5 4 tRP 20ns 3 2 2 tRRD 20ns 2 2 2 tRCD 20ns 3 2 2 tCCD 10ns 1 1 1 tCDL 10ns 1 1 1 tRDL 10ns 1 1 1
125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns)
CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHz SDRAM (Unit = number of clock)
Frequency CAS Latency 3 2 tRC 70ns 7 6 tRAS 50ns 5 5 tRP 20ns 2 2 tRRD 20ns 2 2 tRCD 20ns 2 2 tCCD 10ns 1 1 tCDL 10ns 1 1 tRDL 10ns 1 1
100MHz (12.0ns) 83MHz (12.0ns)
REFRESH CYCLE PARAMETERS
-10 Parameter Refresh Period (1,2) Symbol tREF Min -- Max 64 Min -- -12 Max 64 Units ms
NOTES: 1. 4096 cycles 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device.
SDRAM COMMAND TRUTH TABLE
Function Mode Register Set Auto Refresh (CBR) Precharge Bank Activate Write Write with Auto Precharge Read Read with Auto Precharge Burst Termination No Operation Device Deselect Data Write/Output Disable Data Mask/Output Disable Single Bank Precharge all Banks SDCE L L L L L L L L L L L H X X SDRAS L L L L L H H H H H H X X X SDCAS L L H H H L L L L H H X X X SDWE L H L L H L L L H L H X X X BWE X X X X X X X X X X X X L H X BA X BA BA BA BA BA X X X X X A12, A13 SDA10 A11-0 Notes
OP CODE X L H Row Address L H L H X X X X X 4 4 2 2 2 2 2 3 2
NOTES: 1. All of the SDRAM operations are defined by states of SDCE\, SDWE\, SDRAS\, SDCAS\, and BWE0-3 at the positive rising edge of the clock. 2. Bank Select (BA), if A12 (BA0) and A13 (BA1) select between different banks. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
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MODE REGISTER SET TABLE
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
BT Burst Length
*Should program M11, M10 = "0, 0" to ensure compatibility with future devices.
Burst Length M2 M1 M0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved
M3 0 1
Burst Type Sequential Interleaved
M2 M1 M0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
M8 0 ---
M7 0 ---
M6-M0 Defined ---
Operating Mode Standard Operation All other states reserved
M9 0 1
Write Burst Mode Programmed Burst Length Single Location Access
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SDRAM CURRENT STATE TRUTH TABLE
Current State SDCE L L L L Idle L L L L H L L L L Row Active L L L L H L L L L Read L L L L H L L L L Write L L L L H L L L Read with Auto Precharge L L L L L H SDRAS L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X SDCAS L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X SDWE L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X Command A12 & A13 (BA) A11-A0 Description Mode Register Set X X Row Address Column Column X X X Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Action Set the Mode Register Start Auto No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst 2 2 2 5,6 5,6 2 5,6 5,6 3 1 4,5 4,5 2 1 1 Notes 1 1
OP Code
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SDRAM CURRENT STATE TRUTH TABLE (cont.)
Current State SDCE L L L Write with Auto Precharge L L L L L H L L L L Precharging L L L L H L L L L Row Activating L L L L H L L L L Write Recovering L L L L H L L L Write Recovering with Auto Precharge L L L L L H SDRAS L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X SDCAS L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X SDWE L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X Command A12 & A13 (BA) A11-A0 Description Mode Register Set X X Row Address Column Column X X X Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD No Operation; Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL No Operation; Row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL 2 2 2,6 2,6 2 2 6 6 2 2 2 2 2 2 20 2 2 Notes
OP Code
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SDRAM CURRENT STATE TRUTH TABLE (cont.)
Current State SDCE L L L L Refreshing L L L L H L L L Mode Register Accessing L L L L L H SDRAS L L L L H H H H X L L L L H H H H X SDCAS L L H H L L H H X L L H H L L H H X SDWE Command A12 & A13 A11-A0 (BA) L OP Code H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X X X Row Address Column Column X X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles Notes
NOTES: 1. Both Banks must be idle otherwise it is an illegal action. 2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 3. The minimum and maximum Active time (tRAS) must be satisfied. 4. The RAS to CAS Delay (tRCD) must occur before the command is given. 5. Address SDA10 is used to determine if the Auto Precharge function is activated. 6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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FIG. 5
SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @ CAS LATENCY = 3, BURST LENGTH = 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
SDCLK
tCC
tCH
tCL tRCD tRAS
SDCE
tRCD
tSS
tSH
tRP
tSS
SDRAS
tSH
tSS
SDCAS
tSH
tCCD
tSS
ADDR Ra
tSH
Ca
tSS
Cb
tSH
Cc Rb
Note 2, 3
Note 2, 3
Note 2, 3 Note 4
Note 2
BA
BS
BS
BS
BS
BS
BS
SDA10
Ra
Note 3
Note 3
Note 3
Note 4
Rb
tRAC tSAC
DQ
Qa
tSS
Db
tSH
Qc
tSLZ
SDWE
tOH
tSS
tSH
tSS
BWE
tSH
Row Active
Read
Write
Read Precharge
Row Active
DON'T CARE
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FIG. 6
SDRAM POWER UP SEQUENCE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE
tRP
SDRAS
tRFC
tRFC
SDCAS
ADDR
Key
RAa
BA
SDA10
RAa
DQ
HIGH-Z
SDWE
BWE
High level is necessary
Precharge (All Banks)
Auto Refresh
Auto Refresh
Mode Register Set Row Active (A-Bank)
DON'T CARE
January 20001
15
White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
WED9LC6416V
FIG. 7
SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
Note 1
tRC
SDCE
tRCD
SDRAS
SDCAS
ADDR
Ra
Ca0
Rb
Cb0
BA
SDA10
Ra
Rb
Note 3
tRAC
tSHZ tSAC
Qa0
Note 4
tOH
Qa1 Qa2 Qa3 Db0 Db1 Db2
tRDL
Db3
CL = 2 DQ CL = 3
tRAC
Note 3
tSAC
Qa0
tOH
Qa1 Qa2
tSHZ
Qa3
Note 4
tRDL
Db0 Db1 Db2 Db3
SDWE
BWE
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
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16
January 2001
WED9LC6416V
FIG. 8
SDCLK
SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
SDCE
tRCD
SDRAS
Note 2
SDCAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
SDA10
Ra
tRDL
CL = 2 DQ CL = 3 Qa0 Qa1 Qb0 Qb1 Dc0 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1
tCDL
Dc1 Dd0 Dd1
SDWE
Note 1
Note 3
BWE
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. To write data before burst read ends. BWE should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written. 3. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
January 20001
17
White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
WED9LC6416V
FIG. 9
SDCLK
SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Note 1
SDCE
SDRAS
Note 2
SDCAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
BA
SDA10
RAa
RBb
CL = 2 DQ CL = 3
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2 QBb3
QAc0
QAc1
QBd0
QBd1 QAe0
QAe1
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0 QBd1
QAe0
QAe1
SDWE
BWE
Row Active (A-Bank)
Row Active (B-Bank) Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. SDCE can be "don't care" when SDRAS, SDCAS and SDWE are high at the clock going high edge. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
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18
January 2001
WED9LC6416V
FIG. 10
0
SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
SDCLK
SDCE
SDRAS
Note 2
SDCAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
BA
SDA10
RAa
RBb
tCDL
DQ
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
tRDL
DBd1
SDWE
Note 1
BWE
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank)
Write (B-Bank)
Write (A-Bank)
Write (B-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. To interrupt burst write by Row precharge, BWE should be asserted to mask invalid input data. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
January 20001
19
White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
WED9LC6416V
FIG. 11
0
SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
SDCLK
SDCE
SDRAS
SDCAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
SDA10
RAa
RBb
RAc
tCDL
CL = 2 DQ CL = 3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3
Note 1
QAc0
QAc1
QAc2
QAc0
QAc1
SDWE
BWE
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Row Active (B-Bank)
Write (B-Bank) Row Active (A-Bank)
Read (A-Bank)
DON'T CARE
NOTES: 1. tCDL should be met to complete write.
White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
20
January 2001
WED9LC6416V
FIG. 12
0 SDCLK
SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH = 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
SDCE
SDRAS
SDCAS
ADDR
Ra
Rb
Ca
Cb
BA
SDA10
Ra
Rb
CL = 2 DQ CL = 3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
SDWE
BWE
Row Active (A-Bank)
Read with Auto Precharge (A-Bank) Row Active (B-Bank)
Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
DON'T CARE
NOTES: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2 and BRSW mode)
January 20001
21
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WED9LC6416V
FIG. 13 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH = FULL PAGE
0 SDCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
SDCE
SDRAS
SDCAS
ADDR
RAa
CAa
CAb
BA
SDA10
RAa
Note 2
1
1
CL = 2 DQ
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
2
2
CL = 3
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
SDWE
BWE
Row Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is the same as the case of SDRAS interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on each of them. But at burst write, burst stop and SDRAS interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at every burst length.
White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
22
January 2001
WED9LC6416V
FIG. 14
SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @ BURST LENGTH = FULL PAGE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
SDCLK
SDCE
SDRAS
SDCAS
ADDR
RAa
CAa
CAb
BA
SDA10
RAa
tBDL
tRDL
Note 2
DQ
DAa0
DAa1
DAa2
DAa3
DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
SDWE
BWE
Row Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. BWE at write interrupt by precharge command is needed to prevent invalid write. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length.
January 20001
23
White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
WED9LC6416V
FIG. 15
0
SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
SDCLK
SDCE
SDRAS
Note 2
SDCAS
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
SDA10
RAa
RBb
RAc
CL = 2 DQ CL = 3
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
SDWE
BWE
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank) Read with Auto Precharge (A-Bank)
Row Active (A-Bank) Write with Auto Precharge (B-Bank)
Read (A-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. BRSW modes enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at Write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
24
January 2001
WED9LC6416V
FIG. 16
SDRAM MODE REGISTER SET CYCLE
0 1 2 3 4 5 6
SDRAM AUTO REFRESH CYCLE
0 1 2 3 4 5 6 7 8 9 10
SDCLK
SDCE
Note 2
HIGH
tRFC
SDRAS
Note 1
SDCAS
Note 3
ADDR
Key
Ra
DQ
HI-Z
HI-Z
SDWE
BWE
MRS
New Command
Auto Refresh
New Command
DON'T CARE
*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle. NOTES: MODE REGISTER SET CYCLE 1. SDCE, SDRAS, SDCAS & SDWE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new SDRAS activation. 3. Please refer to Mode Register Set Table.
January 20001
25
White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
WED9LC6416V
PACKAGE DESCRIPTION:
JEDEC MO-163
153 LEAD BGA (17 x 9 BALL ARRAY)
3.50 (0.138) MAX
14.00 (0.551) BSC
A B C D E F G H J K L M N P R T U
PIN 1 INDEX
22.00 (0.866) BSC
1.27 (0.050) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
COMMERCIAL (0C TA 70C) INDUSTRIAL (-40C TA 85C)
Part Number WED9LC6416V2012BC WED9LC6416V2010BC WED9LC6416V1612BC WED9LC6416V1610BC WED9LC6416V1512BC WED9LC6416V1510BC WED9LC6416V1312BC WED9LC6416V1310BC
SSRAM Access 200MHz 200MHz 166MHz 166MHz 150MHz 150MHz 133MHz 133MHz
SDRAM Access 125MHz 100MHz 125MHz 100MHz 125MHz 100MHz 125MHz 100MHz
Part Number WED9LC6416V2012BI WED9LC6416V2010BI WED9LC6416V1612BI WED9LC6416V1610BI WED9LC6416V1512BI WED9LC6416V1510BI WED9LC6416V1312BI WED9LC6416V1310BI
SSRAM Access 200MHz 200MHz 166MHz 166MHz 150MHz 150MHz 133MHz 133MHz
SDRAM Access 125MHz 100MHz 125MHz 100MHz 125MHz 100MHz 125MHz 100MHz
White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
26
January 2001
WED9LC6416V
FIG. 17
INTERFACING THE TEXAS INSTRUMENTS TMS320C6x WITH THE WED9LC6416V (128Kx32 SSRAM/4Mx32 SDRAM)
Address Bus EA2-21
Texas Instruments TMS320C6x DSP
SSWE\ CE2\ SSOE\ SSADS\ SSCLK BE0\ BE1\ BE2\ BE3\ SDA10 CE0\ SDRAS\ SDCAS\ SDWE\ SDCLK
EA2 A0 EA3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
WED9LC6416V
128K x 32 SSRAM 4M x 32 SDRAM
DQ0-7 DQ8-15 DQ16-23 DQ24-31
SSWE\ SSCE\ SSOE\ SSADC\ SSCLK BWE0\ BWE1\ BWE2\ BWE3\ SDA10 SDCE\ SDRAS\ SDCAS\ SDWE\ SDCLK
SSRAM Control
Shared Controls
Data Bus ED0-31
SDRAM Control
January 20001
27
White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com

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